Design Exploration of EMBRACE Hardware Spiking Neural Network Architecture and Applications
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The operation and structure of the human brain has inspired the development of next generation smart embedded computing systems. The cognitive abilities of the human brain have been partially explained by the dense and complex interconnection of neurons and synapses, where each neuron connects to thousands of other neurons and communicates through short transient pulses (spikes) along synaptic links. Brain-inspired computing paradigms such as Spiking Neural Networks (SNNs) mimic the key functions of the human brain and have the potential to offer smart and adaptive solutions for complex real world problems. The main design challenges for the realisation of practical hardware SNN systems are large scale simulation and performance measurement, compact hardware implementation, architectural scalability, application reliability, low power consumption, efficient and accurate SNN learning/training algorithms, compact implementation of complex neural models, fault tolerance and application design methodologies. This thesis contributes to the development of EMBRACE, a compact, scalable, modular, hardware SNN architecture, as an embedded computing platform. The thesis presents a prototype implementation of the EMBRACE architecture on a Xilinx Virtex-6 FPGA and demonstrates reliable, practical embedded classifier and control applications. The thesis contributes to a number of hardware SNN system design challenges such as hardware SNN simulations and performance measurement, compact hardware implementation, architectural scalability, application reliability and efficient practical application design. The research is organised in four distinct phases as follows: Simulation andPerformanceMeasurement ofHardware SNNSystems: The thesis presents EMBRACE-SysC, a SystemC simulation-based design exploration framework for Network on Chip (NoC) based hardware SNN architectures. EMBRACE-SysC incorporates performance measurement and reporting capabilities including spike communication infrastructure, neuron model validation, hardware architecture design exploration and SNN application evolution, used in later phases of this research. Architectural Techniques for Scalability: The storage of large synaptic connectivity information in hardware SNNs translates to poorly scalable, large distributed on-chip memory in hardware SNN architectures. Inspired by the modular organisation of the human brain, this thesis presents a hardware Modular Neural Tile (MNT) architecture that reduces the memory requirement of the architecture using a combination of fixed and configurable synaptic connections. The silicon footprint of the architecture is reduced by an average of 66% for practical SNN application topologies, as compared to the previously reported EMBRACE architecture. Interconnect Architecture for SNN Application Reliability: Distortion in spike timings impacts the accuracy of SNN operation by modifying the precise ring time of neurons within the SNN. The thesis presents an in-depth, simulation-based analysis of the synaptic information jitter in NoC based hardware SNNs. The thesis presents a ring topology NoC architecture using a timestamped, spike broadcast flow control technique that offers fixed spike transfer latency under various network traffic conditions, to provide reliable SNN application behaviour. Modular Application Design: Efficient implementation and training of large scale embedded applications on hardware SNN architectures poses a serious challenge due to the lack of suitable application design methodologies. _e thesis presents the modular application design of a robotic navigational controller application implemented on the EMBRACE FPGA prototype. Results indicate faster application evolution as compared to monolithic application SNNs. The stepwise knowledge integration and simplified SNN training facilitate rapid application prototyping.
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