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Fixed latency on-chip interconnect for hardware spiking neural network architectures

dc.contributor.authorPande, Sandeep
dc.contributor.authorMorgan, Fearghal
dc.contributor.authorSmit, Gerard
dc.contributor.authorBruintjes, Tom
dc.contributor.authorRutgers, Jochem
dc.contributor.authorMcGinley, Brian
dc.contributor.authorCawley, Seamus
dc.contributor.authorHarkin, Jim
dc.contributor.authorMcDaid, Liam
dc.date.accessioned2018-09-20T16:21:03Z
dc.date.available2018-09-20T16:21:03Z
dc.date.issued2013-09-01
dc.identifier.citationPande, Sandeep; Morgan, Fearghal; Smit, Gerard; Bruintjes, Tom; Rutgers, Jochem; McGinley, Brian; Cawley, Seamus; Harkin, Jim; McDaid, Liam (2013). Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel Computing 39 (9), 357-371
dc.identifier.issn0167-8191
dc.identifier.urihttp://hdl.handle.net/10379/13396
dc.publisherElsevier BV
dc.relation.ispartofParallel Computing
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Ireland
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/3.0/ie/
dc.subjectnetwork on chip (noc)
dc.subjectspiking neural networks (snn)
dc.subjectsynaptic connectivity
dc.subjectlatency jitter
dc.subjectneurons
dc.subjectimplementations
dc.subjectplatform
dc.subjectdesign
dc.titleFixed latency on-chip interconnect for hardware spiking neural network architectures
dc.typeArticle
dc.identifier.doi10.1016/j.parco.2013.04.010
dc.local.publishedsourcehttps://ris.utwente.nl/ws/files/6866866/rnoc_pc_submitted-1.pdf
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Except where otherwise noted, this item's license is described as Attribution-NonCommercial-NoDerivs 3.0 Ireland